Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
The geometry of structures fabricated on a semiconductor wafer depends on process conditions during lithographic exposure. Process parameters such as focus, dose, and scanner aberration affect the shape of the resulting structures differently, depending on the type of structure being fabricated. For example, relatively isolated structures are more sensitive to focus changes, while relatively dense structures are more sensitive to changes in dosage. Device functionality and manufacturing yield is limited by the quality of the structures formed by patterning steps, e.g., lithography, deposition, etch, etc.
Metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. Optical metrology techniques offer the potential for high throughput without the risk of sample destruction. A number of optical metrology based techniques including scatterometry and reflectometry implementations and associated analysis algorithms are commonly used to characterize critical dimensions, film thicknesses, composition, overlay and other parameters of nanoscale structures.
Existing model based metrology methods typically include a series of steps to model and then measure structure parameters. Typically, measurement data is collected (e.g., DOE spectra) from a particular metrology target. An accurate model of the optical system, dispersion parameters, and geometric features is formulated. Film spectra measurements are collected to determine material dispersions. A parametric geometric model of the target structure is created along with an optical model. In addition, simulation approximations (e.g., slabbing, Rigorous Coupled Wave Analysis (RCWA), etc.) must be carefully performed to avoid introducing excessively large errors. Discretization and RCWA parameters are defined. A series of simulations, analysis, and regressions are performed to refine the geometric model and determine which model parameters to float. A library of synthetic spectra is generated. Finally, measurements are performed using the library and the geometric model. Each step introduces errors and consumes a significant amount of computational and user time. Typically, a model building task requires days, or even weeks, to complete. In addition, the size of the library and the computation time associated with performing regression calculations during measurement reduces the throughput of the measurement system.
In addition, conventional metrology techniques rely on dedicated metrology structures or targets. In semiconductor manufacture, and patterning processes in particular, process control is enabled by performing metrology on specific dedicated structures. These dedicated structures may be located in the scribe lines between dies, or within the die itself. The use of dedicated metrology structures may introduce significant measurement errors.
Discrepancies between actual device structures and dedicated metrology targets limit the ability of metrology data to accurately reflect the status of the actual device features in the die. In one example, discrepancies arise due to location dependent differences in process loading, pattern density, or aberration fields because the dedicated metrology targets and actual device structures are not collocated. In another example, the characteristic feature sizes of the dedicated metrology structures and the actual device structure are often quite different. Hence, even if the dedicated metrology target and the actual device structure are in close proximity, discrepancies result from differences in size.
In some examples, CD-SEM is used for hot spot monitoring, but CD-SEM suffers from low throughput and insufficient precision that makes it unsuitable for inline, high throughput metrology. In addition, CD-SEM frequently deforms the pattern undergoing measurement, and thus is not suitable for measuring device structures.
Future metrology applications present challenges due to increasingly small resolution requirements and increasingly complex geometric structures. Methods and systems for improved monitoring of the geometry of a large number of different types of structures during fabrication are desired to identify defects early in the manufacturing process.